The invention lies in the integrated technology field. More specifically, the present invention relates to an integrated memory and a memory configuration having at least a first memory and a second memory and also to a method for operating a memory configuration having at least a first memory and a second memory.
Configurations such as, for example, personal computer systems (PC systems) generally have data processing devices in the form of microprocessors or micro-controllers and functional units such as program memories, data memories or input/output peripheral assemblies. The microprocessor thereby usually constitutes the central control and computation unit and is therefore also referred to as the so-called central processing unit (CPU). The data memory, which is generally embodied as a so-called random access memory (RAM), contains, for example, data which are accessed during a memory access. The electrical connection between the microprocessor and the data memory, for example, is usually established via a bus system.
It can generally be observed that, in order to increase the data throughput, microprocessors are operated with increasing processing speeds and hence increasing transmission frequencies as well. For this reason, in particular, it is endeavored likewise to increase the processing speed and transmission frequency on the corresponding bus systems, in order not to limit the overall performance of the PC system. However, this can generally lead to physical and/or electrical problems. Particularly in the case of comparatively long bus systems connected to a memory configuration having a plurality of memories or memory modules connected in parallel, increasing transmission frequencies can be accompanied by a high degree of reflection and interference of signals to be transmitted. This can impair the signal quality and hence the detect ability of the data to be transferred. This reflection and interference is caused for example by a multiplicity of memory modules connected in parallel and thexe2x80x94as a resultxe2x80x94limited possibilities for suitable matching of the electrical parameters and/or by limited electrical properties of the bus systems and of the connected memory modules.
It is accordingly an object of the invention to provide an integrated memory and a memory configuration having at least a first memory and second memory, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which enables a comparatively high data throughput in each case with good detectability of the data to be transferred being maintained. It is a further object of the present invention to specify a method for operating a memory configuration having at least a first memory and a second memory, by means of which a comparatively high data throughput of the memory configuration, for example to a micro-controller, can be achieved with good detectability of the data to be transferred.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, comprising:
a memory cell array for storing data;
first and second communications interfaces for data transfer each connected to a respective data bus system, and each operable independently of one another;
wherein the memory cell array can be connected to the data bus system for a memory cell access;
a comparison circuit connectible to the first communications interface, the comparison circuit comparing an address of data stored in the memory cell array with an address applied to the first communications interface, and activating the memory cell array for a memory cell access in dependence on a comparison result; and
a control circuit connectible to the comparison circuit and the second communications interface, for forwarding the applied address to the second communications interface in dependence on the comparison result of the comparison circuit.
There is also provided, in accordance with the invention, a memory configuration which comprises two or more memories as outlined above. The first communications interface of a first memory is connected to a communication bus and the second communications interface of the first memory is connected to the first communications interface of the second memory.
With the above and other objects in view there is also provided, in accordance with the invention, a method of operating a memory configuration having at least a first memory for storing data, first and second communications interfaces for data transfer to and from the first memory, and having a second memory for storing data, first and second communications interfaces for data transfer to and from the second memory, wherein the first communications interface of the second memory is connected to the second communications interface of the first memory, the method which comprises:
operating the first and second communications interfaces of the first and second memories independently of one another;
applying an address of requested data from outside the memory configuration to the first communications interface of the first memory;
ascertaining whether the applied address corresponds to an address of data stored in the first memory;
if the applied address corresponds to an address of data stored in the first memory, outputting stored data via the first communications interface of the first memory; and
if the applied address does not correspond to an address of data stored in the first memory, transferring the address of the requested data to the second communications interface of the first memory, receiving the requested data from the first communications interface of the second memory via the second communications interface of the first memory, and outputting the requested data via the first communications interface of the first memory.
The memory according to the invention and the memory configuration according to the invention make it possible to achieve a comparatively high data throughput of data to be transferred. This is achieved in particular by virtue of the fact that the communication bus connected to the first memory and the connection between the first memory and the second memory are electrically decoupled. This makes it possible to operate the communication bus and the bus system between the first memory and the second memory with comparatively high data transmission frequencies.
Moreover, the electrical isolation of the bus systems makes it possible to embody the bus systems in such a way that a no relatively low degree of signal reflection occurs. As a result, the signal quality and hence the transmission frequency, too, can be significantly increased. The memory configuration according to the invention creates so-called point-to-point connections of the bus systems which can be configured in such a way that a relatively low degree of reflection occurs even at relatively high signal frequencies. This makes it possible to increase the signal quality and thus the signal frequency. In addition, the creation of isolated bus systems means that it is not absolutely necessary to raise the electrical requirements made of the bus system connecting the two memories and also the electrical requirements made of the second memory itself or of the interface unit thereof.
The invention makes it possible, in particular, to realize memory systems that, in principle, are as large as desired, without having to reduce the data transmission frequency. The memory configuration according to the invention can, in principle, be expanded by as many memories or memory modules as desired. This constitutes a major advantage primarily for future server realizations, for example for the Internet.
The invention can advantageously be used in a main memory system of a PC system. The latter usually comprises a relatively long memory bus system to which one or more memory modules are connected, the memory modules generally being embodied as so-called RAMs.
The memory according to the invention or the memory configuration according to the invention supports a so-called cache mechanism by virtue of the function of the comparison circuit in conjunction with the control circuit. This means, in particular, in the case where the memory configuration is connected to a micro-controller, for example, that the information currently required by the micro-controller is stored as far as possible in the first memory, whereas information that has not been required for a relatively long time is stored as far as possible in the second memory and is thus removed further from the micro-controller. In the case where information stored in the second memory is required by the micro-controller, it is automatically requested and received, under the control of the control circuit, via the second communications interface of the first memory and output via the first communications interface of the first memory to the micro-controller.
If we assume that a microprocessor or the application running in the microprocessor accesses almost the same information over a relatively long time period, the access time of individual memory accesses is reduced further overall if the information is stored in the first memory. The point-to-point connection between the microprocessor and the first memory can correspondingly be operated at high frequency. For the purpose of a moderate increase in costs, the connection between the first memory and second memory can correspondingly be operated at a lower frequency.
In order to support a cache mechanism of this type, it is therefore expedient for the data received via the second communications interface to be stored in the first memory. As a result, future memory accesses in proximity to the last memory access can be processed more rapidly since the information required last has been moved into the vicinity of the microprocessor. However, realizations are also conceivable wherein required data are transferred directly to the first memory without the data first being stored in the first memory.
In a further advantageous development of the method, the received data are stored in the first memory only after having been output via the first communications interface. As a result, a micro-controller connected to the first memory can continue to work immediately after a memory access. After the memory access, in parallel with other micro-controller accesses, the information required last can be transferred to the first memory and stored there.
In a particularly advantageous embodiment of the method according to the invention, a freely available memory area for storing data is defined in the first memory, which memory area is used for storing data received via the second communications interface. In this case, the memory configuration is preferably operated in such a way that at least one memory area of the first memory is xe2x80x9cemptyxe2x80x9d, that is to say no relevant or request able data which could be accessed are stored in the corresponding memory area prior to the storage of received data.
If data received from the second memory are written to a freely available memory area of the first memory, a freely available memory area is no longer present. For this reason, it is advantageous to subdivide the first memory into a plurality of memory areas, for instance in the form of memory banks, for storing data, to transfer data of one of the memory areas to the second memory and to define this memory area as freely available memory area. In this case, it is preferable to choose data of a memory area which have not undergone a memory access for a relatively long time already. The data of such a memory area are transferred for example when there is no longer a freely available memory area in the first memory.
Furthermore, the invention can advantageously be utilized for repairing defective memory areas of the first memory and/or of the second memory. To that end, the first memory and/or the second memory are/is subdivided into a plurality of memory areas for storing data, one of the memory areas of the first memory and/or of the second memory being inhibited for a data access, for example in the case of defective memory cells. As a result, the memory configuration can reliably continue to be used.
The inhibiting can be implemented directly during production, for example. For this purpose, the relevant memory has, for example, programmable elements for storing an address of a memory area to be deactivated. The programmable elements are advantageously embodied in the form of electrical or metallic fuses. The latter can be severed or programmed for example by means of an electric voltage or a laser beam. A memory area can also be inhibited during operation of the memory configuration. By way of example, if the failure of individual memory cells is detected during operation, the affected memory area can be inhibited for further operation when such defect events occur. This can be implemented for example by setting a corresponding register or by programming electrically programmable elements.
In an advantageous embodiment of the integrated memory according to the invention, the memory cell array of the memory is subdivided into two memory blocks which can be connected to the data bus system independently of one another. This enables an efficient realization of the cache concept. In order to further increase the efficiency, the memory has two data bus systems which are each connected to the first and second communications interfaces and can be operated separately from one another. This makes it possible, in particular, for both communications interfaces to be actively operated simultaneously. By way of example, if a memory access takes place via the first communications interface via one of the data bus systems, data received via the second communications interface can advantageously simultaneously be transferred via the other data bus system to a freely available memory area of the memory. For this purpose, the first communications interface and the second communications interface of the memory are operated in parallel for the data transfer.
In order to support such a method of operation, it is advantageous, moreover, that a freely available memory area is in each case defined simultaneously in the subdivided memory blocks, which can be operated independently of one another and in parallel for writing in and reading out data. This methodology ensures that, in the event of a memory access via the first communications interface to one of the memory blocks, a freely available memory area is available, in each case independently of this, in the other of the memory blocks, to which received data can be written at the same time via the second communications interface.
Since only point-to-point connections occur in the memory configuration according to the invention, the latter can be operated at very high frequencies. In this case, transmission frequencies of as much as 1 GHz appear to be achievable. In this case, it is possible to use memories whose memory cell arrays are subdivided into a different number of memory areas, for example memory banks, which can each be activated separately from one another.
In the memory configuration according to the invention, it is possible, moreover, to use memories which have a different number of memory cells and/or are fabricated using different fabrication technology. In other words, it is possible to combine different memories or memory modules with one another.
In this case, it is advantageous to use for the first memory a particularly fast variant for rapid communication with a micro-controller, which variant can, however, at lower data transfer rates, communicate with memories with a lower frequency and longer memory access time. During the operation of such a memory, the first and second communications interfaces accordingly have different operational speeds during the data transfer. This improves, in particular, the so-called latency for immediately successful memory accesses to the first memory. The overall costs of the memory configuration rise only comparatively moderately, however, since the second memory and, if appropriate, further memories may comply with less stringent requirements. If memories of different size are used in the same memory configuration, the memory chosen as the first memory is, for example, a particularly fast memory which, however, has a comparatively small number of memory cells.
In a further embodiment of the memory configuration, the memories are applied on a common memory module for use in a data processing system. The memory configuration can also be realized by soldering the individual memories directly onto, for example, a so-called motherboard of a PC system.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a Integrated memory and memory configuration having a plurality of memories and method for operating such a memory configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.